This application relates generally to integrated circuit design and simulation and, more particularly, to the use of parametric yield information during analog circuit automatic optimization processes.
Circuit design requires several steps including topology selection, sizing and layout. Topology selection is the task of choosing an interconnection of circuit components and devices to implement a desired function. To size a circuit, current methodologies use simple handcrafted equations and various heuristics to guess at initial values for device sizes. A typical process is shown in FIG. 1a: Beginning with an unsized design at 101, a set of first order equations are solved (103) and a rough design is done by hand (105). Simulation (107) is invoked and device sizes are “tweaked” (111) to rectify the simple, first-order handcrafted equations with more precise simulation until the specifications are met (109), resulting in a sized design (113).
Circuit synthesis replaces this manual, designer-in-the-loop process with automated sizing shown in FIG. 1 b: After taking the unsized design (121) and performing the initial setup (123), an automatic sizing process (125) yields a sized design (127). The simulation environment used in the manual design process is typically a SPICE-type simulation. Examples of commercially available SPICE simulators include the Spectre simulator from Cadence, the Eldo simulator from Mentor Graphics and the HSPICE simulator from Synopsys. Once a circuit has been sized it proceeds to the next step in the design process, layout.
During the fabrication process of integrated circuit, because of physical processing, imperfections in the properties of devices may vary from one to other. This causes measured circuit performance to differ from the results from circuit simulation, causes yield problems. This problem is considered in the idea of Design For Yield (DFY), which is now discussed.
The ratio of number of chips that meet specifications in certain conditions to the total number of chips that are manufactured is defined as yield. There are two types of yield: One is functional yield or catastrophic yield, which measures the percentage of chips having functionality. The other is parametric yield, which measures the percentage of chips meeting all specifications. To maximize the parametric yield of a chip, two types of effects should be considered. One is environmental effects, which includes temperature changes, power supply changes, etc. The other is manufacture-related effects, also called physical process variations. The method to design a robust circuit with respect to environmental changes and process variations is called design for yield or design for parametric yield.
Physical process variations are caused by processing and mask imperfection. Normally these are modeled as two different types of statistical variations in the circuit device model: Global, or inter-die, variation and local variation, mismatch variation or intra-die variation. Design for yield (DFY) has become more and more important in modern technology for high performance analog circuit design because variations in device properties, especially mismatch effects, increase within the shrinking of typical device size. Designing analog circuit or migrating design to 90 nm or newer technology processes will need more design effort to achieve high yield design. There exist various methods to optimize analog circuit yield considering environmental and physical variation, including Worst-Case Corner, Monte Carlo Simulation, Response Surface Model, and Worst Case Distance methods.
Traditional worst-case methods are limited for several reasons. First, unlike most digital circuits, the typical analog circuit has many varied performance specifications and requires a richer set of simulations to qualify. The simple “Fast” device and “Slow” device worst-case corner methods are generally not adequate for analog circuits. Second, within-die variations (mismatch variations) are becoming more important than die-to-die variations (global process variations) for high performance analog circuits in deep-submicron technologies. The number of worst-case corners increases exponentially with the number of parameters that are varied. To consider mismatch effects, simply enumerating and simulating worst-case corners quickly becomes intractable. Furthermore, the so called worst-case corner method does not typically consider the distribution information of parameters and possible correlation between them, and consequently, circuits using this design method often turn out to be either over-designed or under-designed.
The Monte Carlo method is a reliable and popular method used to estimate yield; however, few applications use Monte Carlo results in a systematic way to generate statistical corners or in a well-defined methodology to maximize yield. In other words, the Monte Carlo method is primarily used as a verification step rather than as an integral part of the design process.
Response Surface Models (RSM) can be built for both design variables and statistical variables to help accelerate yield estimation and as part of a methodology to maximize yield. Building RSM processes includes Model Training, Model Selection, and Model Testing process. Model Training is the process to adjust model parameters to minimize model training error. Model selection is the process to selection right model structure and complexity. Model testing is the process to evaluate the quality of the model.
RSM can have high accuracy in low dimensional and weak nonlinear design spaces. The yield estimation process can be accelerated by running Monte Carlo simulations on RSM. Applying direction optimization techniques on some forms of RSM can make design for yield processes easier; for examples, quadratic optimization can be used to quickly find the optimum of quadratic forms in RSM. However, as most analog design spaces are very nonlinear, it is difficult to use Design of Experiment to screen statistical and design variables, as this causes the number of samples needed to build RSM rapidly becomes intractable as the number of variables increase. Also, the error inherent in any RSM is another drawback to this approach, as this error will make yield estimations inaccurate and often fail to find high yield circuit design.
The Worst Case Distance method can be illustrated as follows: assume a linear relation between performance, f, and a statistical variable, s, and assume a Gaussian distribution for the statistical variable s. For performance function, f(s), the performance specification is U. First the performance variance is calculated, then the Worst Case Distance, βW, is calculated. The yield can be estimated by using the Worst Case Distance βW for each performance. Finally the Worst Case parameter and tolerance class can be derived. For nonlinear circuit performance, sensitivity analysis can be use for each performance and it will iterate the Worst Case Distance process until it converges. Worst Case Distance method is easy to implement and fast for yield estimation and optimization. However, sensitivity analysis has limitations for the nonlinear performance functions. Further, although this method is efficient for linear or nearly linear performance functions with a small number of statistical variables, it quickly becomes less efficient for nonlinear performance specifications or for designs with a large number of parameters.
Consequently, although there are some known methods for design for yield, there remains room for improvement, particularly for use in analog circuits and when there are nonlinear characteristics, large numbers of parameters, or both.